Bohan Li

Tel: +86 15975558614
Email: leebrandon@163.com
Website: brandon-lee-bo.github.io

Education

South China University of Technology (SCUT), Guangzhou, China
Sept. 2023 -- Present

B.Eng. in Microelectronics Science and Engineering
GPA: 3.86/4; Ranking: 9%
Relevant Courses: Digital Electronic Circuits, Analog Electronic Circuits, Signals and Systems, Calculus, C++

Research Interests

Hardware-Software Co-Design; LLM for Architecture; Domain-Specific Architectures

Publication

Bohan Li (equal contribution), Shengmin Li (equal contribution), Xinyu Shi, Enyi Yao, Francky Catthoor, Simei Yang. FlexVector: A SpMM Vector Processor with Flexible VRF for GCNs on Varying-Sparsity Graphs. IEEE Transactions on Computers (Under Review). Preprint: https://arxiv.org/abs/2604.10113

Research Experience

Vector Processor Accelerator for GCN Acceleration

South China University of Technology, advised by Prof. Simei Yang
Jul. 2024 -- Apr. 2026

  • Proposed FlexVector, a vector-processor-based SpMM accelerator for GCN inference, featuring a flexible VRF with fixed and dynamic regions to eliminate costly DRAM traffic caused by power-law graph irregularity, in collaboration with Prof. Francky Catthoor (IEEE Fellow).
  • Co-designed a hybrid graph preprocessing strategy (inter-tile edge-cut + intra-tile vertex-cut) and hierarchical dataflow (row-wise product at buffer-VRF level; inner-product at DRAM-buffer level), bridging software-level graph partitioning with hardware lane utilization.
  • Achieved 3.78x speedup and 40.5% lower energy versus a state-of-the-art cache-centric baseline at comparable area cost, evaluated on five real-world GCN datasets.

Intelligent Oscillator Circuit for Micro-Nano Robots

Westlake University, Summer Research Internship, advised by Prof. Wei Wang
Jul. 2025 -- Aug. 2025

  • Identified limitations of existing micro-nano robot circuit designs, including area and oscillation frequency.
  • Designed an intelligent oscillator circuit with externally controllable frequency and amplitude to improve motion efficiency of micro-nano robots, contributing a novel methodology for robot control.

High-Speed Multi-Port Shared Cache Management Module

South China University of Technology
Sept. 2024 -- Nov. 2024

  • Participated in the National College Student Embedded Chip & System Design Competition and the National College Student IC Innovation & Entrepreneurship Competition based on the Vivado development flow.
  • Responsible for implementing a data verification module supporting ECC and CRC, ensuring data transmission.

Awards & Honors

  • Best Poster Award, Summer Research Program, Westlake University (2025)
  • National First & Third Prize, National College FPGA Innovation Design Competition (2024, 2025)
  • National Third Prize & South China First Prize, National College IC Innovation Competition (2024)
  • Second-Class Scholarship, South China University of Technology (2024, 2025)

Skills

  • Technical: Codex, Claude Code, GitHub, Verilog, Python, LaTeX, Synopsys Design Compiler, Vivado, CACTI
  • Languages: Mandarin Chinese (native), English (IELTS 6.5)